1. Field of the Invention
The present invention relates generally to the field of integrated circuit application and, more particularly, to the field of integrated circuit memory devices.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Microprocessor controlled integrated circuits are used in a wide variety of applications. Such applications include personal computers, vehicle control systems, telephone networks, and a host of consumer products. As is well known, microprocessors are essentially generic devices that perform specific functions under the control of the software program. This program is stored in a memory device which is coupled to the microprocessor. Not only does the microprocessor access memory devices to retrieve the program instructions, but it also stores and retrieves data created during execution of the program in one or more memory devices.
There are a variety of different memory devices available for use in microprocessor-based systems. The type of memory device chosen for a specific function within a microprocessor-based system depends largely upon what features of the memory are best suited to perform the particular function. Memory manufacturers provide an array of innovative fast memory chips for various applications. While both Dynamic Random Access Memories (DRAM) and Static Random Access Memories (SRAM) are making significant gains in speed and bandwidth, even the fastest memory devices can not match the speed requirements of the microprocessors. The solution for providing adequate memory bandwidth depends on system architecture, the application requirements, and the processor, all of which help determine the best memory type for a given application. Limitations on speed include delays in the chip, the package, and the system. Thus, significant research and development has been devoted to finding faster ways to access memory.
Also of concern to researchers has been developing new ways to get more and more capabilities into smaller areas. Engineers have been challenged with finding ways to increase hardware capabilities, with memory capacity being one area in which board geography is at a particular premium. Increasing memory capability while reducing the amount of layout space that the memory components require presents developers with a considerable challenge.
Another type of memory device is a standard Synchronous Dynamic Random Access Memory (SDRAM). Synchronous control means that the DRAM latches information from the processor under the control of a system clock. The processor can be told how many clock cycles it takes for the DRAM to complete its task, so it can safely implement other tasks while the DRAM is processing its request.
One technique for increasing the speed of a synchronous DRAM is called “prefetch.” In this case more than one data word is fetched from the memory on each address cycle and transferred to a data selector on an output buffer. Multiple words of data can then be sequentially clocked out for each address access. The main advantage of this approach is that, for any given technology, data can be accessed at multiples of the clock rate of the internal DRAM.
There are also some drawbacks to a prefetch type of architecture. An output register must be added to the chip to hold the multiple words that are prefetched. Disadvantageously, this adds to the chip size. If more than two address bits (two data words) are prefetched, it adds considerably to the chip size but ensures a fast unbroken data stream. An eight-bit prefetch scheme, for example, can achieve a very high frequency of operation for long bursts but it adds a considerable amount of chip area. In addition the power consumption may disadvantageously increase if random addressing is required due to data thrashing.
A two-bit prefetch scheme adds a conventionally acceptable increase in the chip size for narrow I/O width memories. For wide word I/O memories, such as ×32 I/O widths, even a two word prefetch scheme may have an unacceptable die size penalty. With a two-bit prefetch, however, there are limitations on the timing. New column addresses can only occur on alternate cycles since there are always two address bits generated for every access.
The present invention may address one or more of the problems set forth above.